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information in this document is provided solely to enable use of intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. information contained herein supersedes previously published specifications on these devices from intel . ? intel corporation 1999, 2000 february 2000 order number: 245101-002 celeron ? processor mobile module: mobile module connector 1 (mmc-1) at 466 mhz and 433 mhz datasheet product features n mobile celeron ? processor with core frequency running at 433 mhz and 466 mhz n 128k of on-die 2 nd level cache n 66-mhz processor system bus speed n integrated active thermal feedback (atf) system ? acpi rev. 1.0 compliant ? internal a/d?digital signaling (smbus) across the module interface ? programmable trip point interrupt or poll mode for temperature reading n processor core voltage regulation supports input voltages from 5v to 21v ? above 80 percent peak efficiency n a thermal transfer plate on the cpu and the intel a 82433dx for heat dissipation n intel 82443dx host bridge system controller ? dram controller supports edo and sdram at 3.3v ? supports pci clkrun# protocol ? sdram clock enable support and self refresh of edo or sdram during suspend mode ? 3.3v only pci bus control, rev 2.1 compliant
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life-saving, or life-sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the celeron processor mobile modules may contain design defects or errors known as errata. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained by calling 1-800- 548-4725 or by visiting intel?s web site at http://www.intel.com copyright ? intel corporation1999, 2000. *other brands and names are the property of their respective owners.
i celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz contents 1.0 introduction ................................ ........................... 1 1.1 revision history ................................ .................... 1 2.0 architecture ove rview ................................ ...... 1 3.0 connector interf ace ................................ .......... 3 3.1 signal definition ................................ .................... 3 3.1.1 signal list ................................ ....................... 4 3.1.2 memory (108 signals) ................................ ..... 5 3.1.3. pci (56 signals) ................................ .............. 6 3.1.4 processor and piix4e/m sideband (9 signals) 6 3.1.5 power management (8 signals) ...................... 8 3.1.6 clock (8 signals) ................................ ............. 9 3.1.7 voltages (39 signals) ................................ .... 10 3.1.8 jtag (7 signals) ................................ .......... 10 3.1.9 miscellaneous (45 signals) ........................... 11 3.2 connector pin assignments ................................ 12 3.3 pin and pad assignments ................................ ... 14 4.0 functional descr iption ................................ .... 15 4.1 celeron processor mobile module mmc-1 .......... 15 4.2 l2 cache ................................ ............................ 15 4.3 the 82443dx host bridge system controller ..... 15 4.3.1 memory organization ................................ ... 15 4.3.2 reset strap options ................................ ..... 15 4.3.3 pci interface ................................ ................. 16 4.3.4 agp feature set ................................ ........... 16 4.4 power management ................................ ............ 16 4.4.1 clock control architecture ............................ 16 4.4.2 normal state ................................ ................. 18 4.4.3 auto halt state ................................ .............. 18 4.4.4 stop grant state ................................ ........... 18 4.4.5 quick start state ................................ ........... 18 4.4.6 halt/grant snoop state .............................. 18 4.4.7 sleep state ................................ ................... 18 4.4.8 deep sleep state ................................ .......... 19 4.5 typical pos/str power .............................. 19 4.6 electrical requirements ................................ ...... 19 4.6.1 dc requirements ................................ ......... 19 4.6.2 ac requirements ................................ .......... 21 4.6.2.1 bclk signal quality sp ecifications and measurement guidelines .......... 22 4.7 the voltage regulator ................................ ........ 22 4.7.1 voltage regulator efficiency ......................... 22 4.7.2. control of the voltage regulator ................... 23 4.7.2.1 voltage signal definition and sequencing ................................ ...... 24 4.7.3 power planes: bulk capacitance requirements ................................ ................ 25 4.7.4 surge current guidelines ............................. 26 4.7.4.1 sl ew-rate control: circuit description ................................ ......................... 28 4.7.4.2 undervoltage lockout: circuit description (v_uv_lockout) .............. 29 4.7.4.3 overvoltage lockout: circuit description (v_ov_lockout) .............. 30 4.7.4.4 overcurrent protection: circuit description ................................ ....... 30 4.8 active thermal feedback ................................ ... 30 4.9 thermal sensor configuration register .............. 31 5.0 mechanical speci fication ................................ 31 5.1 module dimensions ................................ ............ 31 5.1.1 mmc-1 connector pin 1 location ................. 32 5.1.2 printed circuit board thickness .................... 32 5.1.3 height restriction s ................................ ....... 33 5.2 thermal transfer plate ................................ ........ 33 5.3 physical support ................................ ................. 35 5.3.1 mounting requirements ................................ 35 5.3.2 module weight ................................ .............. 36 6.0 thermal specific ation ................................ ...... 36 6.1 thermal design power ................................ ....... 36 6.2 thermal sensor setpoint ................................ .... 36 7.0 labeling informa tion ................................ ....... 37 8.0 environme ntal standards .............................. 38
ii celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz figures figure 1. block diagram of the celeron processor mobile module mmc-1 ................................ ........... 2 figure 2. 280-pin connector footprint pad numbers, module secondary side ................................ ....... 14 figure 3. clock control states ................................ ............ 17 figure 4. bclk, tck, picclk generic clock waveform at the processor core pin ................................ ........ 22 figure 5. power-on sequence timing ................................ . 25 figure 6. instantaneous in-rush current model ................... 26 figure 7. instantaneous in-rush current ............................. 27 figure 8. over current protection circuit ............................ 28 figure 9. spice simulation using in-rush protection (example only) ................................ .................... 29 figure 10. celeron processor mobile module mmc-1 board dimensions ................................ ........................ 31 figure 11. celeron processor mobile module mmc-1 board dimens ions- pin 1 orientation ............................ 32 figure 12. printed circuit board thickness ......................... 33 figure 13. keep-out zone ................................ ................... 33 figure 14. thermal transfer plate (a) ................................ 34 figure 15. thermal transfer plate (b) ................................ 35 figure 16. standoff holes, board edge clearance, and emi containment ring ................................ .............. 36 figure 17. product tracking code ................................ ...... 37 tables table 1. module connector signal summary ........................ 3 table 2. memory signal descriptions ................................ ... 5 table 3. pci signal description ................................ ............ 6 table 4. processor/piix4e/m sideband signal descriptions ................................ ............................ 7 table 5. power management signal descriptions ................ 8 table 6. clock signal descriptions ................................ ....... 9 table 7. voltage descriptions ................................ ............. 10 table 8. jtag pins ................................ ............................. 10 table 9. miscellaneous pins ................................ ............... 11 table 10. connector pin assignments ................................ 12 table 11. connector specifications ................................ .... 15 table 12. configuration straps for the 82443dx host bridge system controller ................................ ............... 16 table 13. clock state characteristics ................................ . 19 table 14. pos/str power ................................ ................. 19 table 15. power supply design specifications .................. 19 table 16. ac specifications (bclk) at the processor core pins ................................ ................................ ..... 21 table 17. bclk signal quality specifications at the processor core ................................ ................... 22 table 18. typical voltage regulator efficiency ................... 22 table 19. voltage signal definitions and sequences ......... 24 table 20. vr_on in-rush current ................................ ...... 25 table 21. capacitance requirements per power plane ...... 26 table 22. thermal sensor smbus address table .............. 30 table 23. thermal sensor configuration register .............. 31 table 24. thermal design power specifications ................ 36 table 25. environmental standards ................................ .... 38
1 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 1.0 introduction this document provides the technical information for integrating the celeron ? processor mobile module connector 1 (mmc-1) into the latest notebook systems for today?s notebook market. building around this modular design gives the system manufacturer these advantages: avoids complexities associated with designing high- speed processor core logic boards. provides an upgrade path from previous intel mobile modules using a standard interface. 1.1 revision history date revision updates 3/1999 1.0 initial release. 2/2000 3.0 updated table 22 2.0 architecture overview the celeron processor mobile module mmc-1 is a highly integrated assembly containing the mobile celeron processor and its immediate system-level support. the celeron processor mobile module mmc-1 offers speeds of 466 megahertz and 433 megahertz. all processor speeds have a 66-megahertz processor system bus (psb) speed. the piix4e/m pci/isa bridge is one of two large-scale integrated devices of the intel 440dx pciset. a notebook?s system electronics must include a piix4e/m device to connect to the celeron processor mobile module. the piix4e/m provides extensive power management capabilities and supports the second integrated device, the intel a 82443dx host bridge. key features of the intel 82443dx host bridge system controller include the dram controller, which supports edo at 3.3 volts with a burst read at 7-2-2-2 (60 nanoseconds) or sdram at 3.3 volts with a burst read at 8-1-1-1 (66 megahertz, cl=2). the 82443dx host bridge also regulates the pci clock on the pci bus. the 82443dx clock enables self refresh mode of edo or sdram during suspend mode and is compatible with smram (c_smram) and extended smram (e_smram) modes of power management. e_smram mode supports write-back cacheable smram up to 1 megabyte. a thermal transfer plate (ttp) on the 82443dx host bridge and the cpu provides heat dissipation and a thermal attach point for the notebook manufacturer?s thermal solution. an on-board voltage regulator converts the system dc voltage to the processor?s core and i/o voltage. isolating the processor voltage requirements allows the system manufacturer to incorporate different processor variants into a single notebook system. supporting input voltages from 5 volts to 21 volts, the processor core voltage regulator enables an above 80 percent peak efficiency and decouples processor voltage requirements from the system. the celeron processor mobile module mmc-1 also incorporates active thermal feedback (atf) sensing, compliant to the acpi specification rev 1.0 . a system management bus (smbus) supports the internal and external temperature sensing with programmable trip points.
2 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz figure 1 illustrates the block diagram of the celeron processor mobile module mmc-1. 280-pin connector cpu volt. reg. pci bus memory bus pclk1 443dx v_3 hclk0 piix4e/m sidebands atf sense smbus psb mobile celeron processor core r_gtl dclkwr dclkrd gclki gclko smbus dclko v_cpuio 2.5v v_dc 5v-21v processor core voltage figure 1 . block diagram of the celeron processor mobile module mmc-1
3 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 3.0 connector interface this section provides signal group and connector pin information. the signals are defined for compatibility with future intel mobile modules. 3.1 signal definition table 1 provides a list of signals by category and the corresponding number of signals in each category. for proper signal termination, please contact your intel sales representative for further information. table 1 . module connector signal summary signal group number of pins memory 108 pci 56 processor/piix4e/m sideband 9 power management 8 clocks 8 voltage: v_dc 10 voltage: v_3s 20 voltage: v_5 1 voltage: v_3 5 voltage: v_cpuio 3 jtag 7 miscellaneous & module id 5 ground 32 reserved 8 total 280
4 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 3.1.1 signal list the following notations are used to denote the signal type: i input pin o output pin o d open-drain output pin requiring a pullup resistor i d open-drain input pin requiring a pullup resistor i/o d input/open-drain output pin, this pin requires a pullup resistor i/o bi-directional input/output pin the signal description also includes the type of buffer used for a particular signal: gtl+ open-drain gtl+ interface signal pci pci bus interface signals cmos the cmos buffers are low voltage ttl compatible signals wi th 3.3-volt outputs and 5.0-volt tolerant inputs.
5 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 3.1.2 memory (108 signals) table 2 lists the memory interface signals. table 2 . memory signal descriptions name type voltage description mecc[7:0] i/o cmos v_3 m emory ecc d ata: these signals carry memory ecc data during access to dram. these pins are not implemented on the mmc-1 connector. rasa[5:0]# or csa[5:0]# o cmos v_3 row address strobe (edo): these pins select the dram row. chip select (sdram): these pins activate the sdrams. sdram accepts any command when its cs# pin is active low. casa[7:0]# or dqma[7:0] o cmos v_3 column address strobe (edo): these pins select the dram column. input/output data mask (sdram): these pins act as synchronized output enables during a read cycle and as a byte mask during a write cycle. mab[9:0]# mab[10] mab[12:11]# mab[13] o cmos v_3 memory address (edo/sdram): this is the row and column address for dram. the 82443dx host bridge system controller has two identical sets of address lines (maa and mab#). the celeron processor mobile module mmc-1 supports only the mab set of address lines. for additional addressing features, please refer to the intel a 440dx pciset datasheet . mwe[a, b]# o cmos v_3 memory write enable (edo/sdram): mwea# should be used as the write enable for the memory data bus. sras[a, b]# o cmos v_3 sdram row address strobe (sdram): when active low, this signal latches row address on the positive edge of the clock. this signal also allows row access and pre- charge. scas[a, b]# o cmos v_3 sdram column address strobe (sdram): when active low, this signal latches column address on the positive edge of the clock. this signal also allows column access. cke[a, b] o cmos v_3 sdram clock enable (sdram): when these signals are deasserted, sdram enters power-down mode. ckeb is nc and not used by the system electronics. md[63:0] i/o cmos v_3 memory data: these signals are connected to the dram data bus. they are not terminated on the celeron processor mobile module mmc-1.
6 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 3.1.3. pci (56 signals) table 3 lists the pci interface signals. table 3 . pci signal description name type voltage description ad[31:0] i/o pci v_3 address/data: the standard pci address and data lines. the address is driven with frame# assertion and data is driven or received in following clocks. c/be[3:0]# i/o pci v_3 command/byte enable: the command is driven with frame# assertion and byte enables corresponding to supplied or requested data is driven on the following clocks. frame# i/o pci v_3 frame: assertion indicates the address phase of a pci transfer. negation indicates that the cycle initiator desires one more data transfer. devsel# i/o pci v_3 device select: the 82443dx host bridge drives this signal when a pci initiator is attempting to access dram. devsel# is asserted at medium decode time. irdy# i/o pci v_3 initiator ready: asserted when the initiator is ready for data transfer. trdy# i/o pci v_3 target ready: asserted when the target is ready for data transfer. stop# i/o pci v_3 stop: asserted by the target to request the master to stop the current transaction. plock# i/o pci v_3 lock: indicates an exclusive bus operation and may require multiple transactions to complete. when lock# is asserted, nonexclusive transactions may proceed. the 82443dx supports lock for cpu initiated cycles only. pci initiated locked cycles are not supported. req[4:0]# i pci v_3 pci request: pci master requests for pci. gnt[4:0]# o pci v_3 pci grant: permission is given to the master to use pci. phold# i pci v_3 pci hold: this signal comes from the expansion bridge; it is the bridge request for pci. the 82443dx host bridge will drain the dram write buffers, drain the processor-to-pci posting buffers, and acquire the host bus before granting the request via phlda#. this ensures that gat timing is met for isa masters. the phold# protocol has been modified to include support for passive release. phlda# o pci v_3 pci hold acknowledge: the 82443dx host bridge drives this signal to grant pci to the expansion bridge. the phlda# protocol has been modified to include support for passive release. par i/o pci v_3 parity: a single parity bit is provided over ad[31:0] and c/be[3:0]#. serr# i/o pci v_3 system error : the 82443dx asserts this signal to indicate an error condition. please refer to the intel a 440bx pciset datasheet for further information. clkrun# i/o d pci v_3 clock run: an open-drain output and input. the 82443dx host bridge requests the central resource ( piix4e/m ) to start or maintain the pci clock by asserting clkrun#. the 82443dx host bridge tri-states clkrun# upon deassertion of reset (since clk is running upon deassertion of reset). pci_rst# i cmos v_3 reset: when asserted, this signal asynchronously resets the 82443dx host bridge. the pci signals also tri-state, compliant with the pci rev 2.1 specifications . 3.1.4 processor and piix4e/m sideband (9 signals) table 4 lists the processor and piix4e/m sideband interface signals. the voltage level for these signals is determined by v_cpuio.
7 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz table 4 . processor/piix4e/m sideband signal descriptions name type voltage description ferr# o cmos v_cpuio numeric coprocessor error : this pin functions as a ferr# signal supporting coprocessor errors. this signal is tied to the coprocessor error signal on the processor and is driven by the processor to the piix4e/m . cpurst n/c cmos v_cpuio processor reset: the signal is not used in the celeron processor mobile module mmc-1. ignne# id cmos v_cpuio ignore error : this open-drain signal is connected to the ignore error pin on the processor and is driven by the piix4e/m . init# id cmos v_cpuio initialization : init# is asserted by the piix4e/m to the processor for system initialization. this signal is an open-drain. intr id cmos v_cpuio processor interrupt : intr is driven by the piix4e/m to signal the processor that an interrupt request is pending and needs to be serviced. this signal is an open-drain. nmi id cmos v_cpuio non-maskable interrupt : nmi is used to force a non-maskable interrupt to the processor. the piix4e/m isa bridge generates nmi when either serr# or iochk# is asserted, depending on how the nmi status and control register is programmed. this signal is an open-drain. a20m# id cmos v_cpuio address bit 20 mask: when enabled, this open-drain signal causes the processor to emulate the address wraparound at 1 mb, which occurs on the intel 8086 processor. smi# id cmos v_cpuio system management interrupt : smi# is an active low synchronous output from the piix4e/m that is asserted in response to one of many enabled hardware or software events. the smi# open-drain signal can be an asynchronous input to the processor. however, in this chip set smi# is synchronous to pclk. stpclk# id cmos v_cpuio stop clock : stpclk# is an active low synchronous open-drain output from the piix4e/m that is asserted in response to one of many hardware or software events. stpclk# connects directly to the processor and is synchronous to pciclk. when the processor samples stpclk# asserted, it responds by entering a low power state (quick start). the processor will only exit this mode when this signal is deasserted.
8 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 3.1.5 power management (8 signals) table 5 lists the power management interface signals. the sm_clk and sm_data signals refer to the two-wire serial smbus interface. although this interface is currently used solely for the digital thermal sensor, the smbus contains reserved serial addresses for future use. see section 4.9 for more details. table 5 . power management signal descriptions name type voltage description oem_pu i cmos v_3 oem pullup: this pullup resistor is not required on the celeron processor mobile module mmc-1 . l2_zz n/c cmos v_cpuio low-power mode for cache sram: this signal is not used on the celeron processor mobile module mmc-1 . sus_stat# i cmos v_3always 1 suspend status: this signal connects to the sus_stat1# outputs of piix4e/m. it provides information on host clock status and is asserted during all suspend states. vr_on i v_3 vr_on: voltage regulator on. this 3.3v (5v tolerant) signal controls the operation of the voltage regulator. vr_on should be generated as a function of the piix4e/m susb# signal, which is used for controlling the ?suspend state b? voltage planes. this signal should be driven by a digital signal with a rise/fall time of less than or equal to 1 us. (vil(max)=0.4v, vih(min)=3.0v). see figure 5, ?power-on sequence timing? for proper sequencing of vr_on. vr_pwrgd o v_3 vr_pwrgd: this signal is driven high to indicate that the voltage regulator is stable and is pulled low using a 100k resistor when inactive. it can be used in some combination to generate the system pwrgood signal. sm_clk i/o d cmos v_3 serial clock: this clock signal is used on the smbus interface to the digital thermal sensor. ensure proper termination based upon the system management bus specification, revision 1.0 . sm_data i/o d cmos v_3 serial data: an open-drain data signal on the smbus interface to the digital thermal sensor. ensure proper termination based upon the system management bus specification, revision 1.0 . atf_int# o d cmos v_3 atf interrupt: this signal is an open-drain output signal of the digital thermal sensor. note: v_3always: 3.3v supply. it is generated whenever v_dc is available and supplied to piix4e/m resume well.
9 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 3.1.6 clock (8 signals) table 6 li sts the clock interface signals. table 6 . clock signal descriptions name type voltage description oem_pd i cmos v_3 oem pulldown: it is renamed from pci_ref and is not required on the module . pclk i pci v_3s pci clock in: pclk is an input to the module from the ckdm66-m clock source and is one of the system?s pci clocks. this clock is used by all of the 82443dx host bridge logic in the pci clock domain. this clock is stopped when the piix4e/m pci_stp# signal is asserted and/or during all suspend states. hclk[1:0] i cmos v_cpuio host clock in: these clocks are inputs to the module from the ckdm66-m clock source and are used by the processor and the 82443dx host bridge system controller. this clock is stopped when the piix4e/m cpu_stp# signal is asserted and/or during all suspend states. susclk n/c cmos v_3 suspend clock : this signal is not used on the module . fqs[1:0] o cmos v_3s frequency status: this signal provides the status of the host clock frequency to the system electronics. these signals are static and are pulled either low or high to the v_3s voltage supply through a 10-k w resistor. this module is designed for the 66-mhz strapping option shown below. fqs1 fqs0 frequency 0 0 60 mhz 0 1 66 mhz 1 0 reserved 1 1 reserved cpu3.3_2.5# o cmos v_cpuio clock voltage select: provides status to the system electronics about the voltage level at which the ckdm66-m clock generator should be operating. this signal is pulled low by module .
10 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 3.1.7 voltages (39 signals) table 7 lists the voltage signal definitions. table 7 . voltage descriptions name type number of pins description v_dc i 10 dc input: 5v-21v. v_3s i 20 susb# controlled 3.3v: v_3s is supplied by the system electronics. this is a 3.3v power supply that is turned off during suspend during system states str, std, and soff. v_5 i 1 susc# controlled 5v: power managed 5v supply. an output of the voltage regulator on the system electronics. this rail is off during std and soff. v_3 i 5 susc# controlled 3.3v: power managed 3.3v supply. an output of the voltage regulator on the system electronics. this rail is off during std and soff. v_cpuio o 3 processor i/o ring: powers the processor interface signals such as the piix4e/m open-drain pullups for the processor/ piix4e/m sideband signals and the ckdm66-m clock source. 3.1.8 jtag (7 signals) table 8 lists the jtag signals, which the system electronics can use to implement a jtag chain and itp port, if desired. the jtag signals provided cannot be used as an itp port, since the itp interface has changed between the generations of the mobile pentium processor and the mobile celeron processor. table 8 . jtag pins name type voltage description tdo o v_cpuio jtag test data out: serial output port. tap instructions and data is shifted out of the processor from this port. tdi i v_cpuio jtag test data in: serial input port. tap instructions and data is shifted into the processor from this port. tms i v_cpuio jtag test mode select: controls the tap controller change sequence. tclk i v_cpuio jtag test clock: testability clock for clocking the jtag boundary scan sequence. trst# i v_cpuio jtag test reset: asynchronously resets the tap controller in the processor. itp(1:0) itp1 itp0 o i v_cpuio debug port signals: these signals are not used in the celeron processor mobile module mmc-1 and should not be connected. note: dbrest# (reset target system) on the itp debug port can be ?logically anded? with vr_pwrgd to piix4e/m?s pwrok.
11 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 3.1.9 miscellaneous (45 signals) table 9 lists the miscellaneous signals. table 9 . miscellaneous pins name type number description module id[3:0] o cmos 4 module revision id : these pins track the revision level of the module. a 100-k pullup resistor to v_3s is required on these signals and should be placed on the system electronics. see section 7.0 for more detail. ppp_pp# o cmos 1 mobile celeron processor or mobile pentium processor present : a high on this signal indicates to the piix4e/m isa bridge config1 pin that the module is based on the pentium pro architecture. a low indicates that the module is of the pentium processor family. this signal is allowed to float on the module and requires a 100-k pullup resistor to v_3s on the system electronics. this signal is grounded. ground i 32 ground. reserved rsvd 8 unallocated reserved pins and should not be connected.
12 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 3.2 connector pin assig nments table 10 lists the signals for each pin of the mmc-1 to the notebook manufacturer?s system electronics. refer to section 3.3, ?pin and pad assignments? for the pin assignments of the pads on the connector. table 10 . connector pin assignments pin number row row row row aa ab ba bb 1 gnd gnd gnd gnd 2 md31 md63 mid0 mid1 3 md30 md61 reserved reserved 4 md29 md62 v_dc v_dc 5 md27 md58 v_dc v_dc 6 v_3s v_3s v_dc v_dc 7 md28 md60 v_dc v_dc 8 md26 md56 v_dc v_dc 9 md25 md57 reserved reserved 10 md24 md59 mid2 mid3 11 gnd gnd gnd gnd 12 cas3#/dqm3 cas7#/dqm7 ad00 frame# 13 cas6#/dqm6 cas2#/dqm2 ad01 lock# 14 ma00 ma01 ad02 devsel# 15 ckea ckeb ad03 irdy# 16 v_3s v_3s v_3s v_3s 17 ma02 ma04 ad04 trdy# 18 ma03 ma05 ad05 stop# 19 md55 md22 ad06 phold# 20 md54 md23 ad07 phlda# 21 gnd gnd gnd gnd 22 md51 md20 ad08 pci_rst# 23 md52 md21 ad09 par 24 md53 md19 ad10 serr# 25 md49 md17 ad11 req0# 26 v_3s v_3s v_3s req1# 27 md48 md18 ad12 req2# 28 md50 md16 ad13 req3# 29 srasa# scasa# ad14 gnt0# 30 srasb# scasb# ad15 gnt1# 31 gnd gnd gnd gnd 32 mwea# mecc3 ad16 gnt2# 33 mweb# mecc7 ad17 gnt3# 34 ras0#/cs0# mecc6 ad18 l2_zz 35 ras1#/cs1# mecc2 ad19 reserved 36 v_3s v_3s v_3s v_3s 37 md14 mecc1 ad20 reserved 38 md11 mecc5 ad21 ppp_pp# 39 md15 mecc4 ad22 clkrun# 40 gnd gnd gnd gnd 41 md10 mecc0 ras2#/cs2# sm_clk 42 md13 md43 ras3#/cs3# sm_data 43 md09 md41 ras4#/cs4# atf_int# 44 md08 md45 ras5#/cs5# susclk 45 v_3s v_3s v_3 v_3 row row row row aa ab ba bb 46 md12 md42 ad23 sus_stat#
13 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 47 ma06 md40 ad24 v_3 48 ma07 md44 ad25 oem_pu 49 ma08 md46 ad26 vr_on 50 gnd gnd gnd gnd 51 ma09 md47 ad27 vr_pwrgd 52 cas1#/dqm1 cas5#/dqm5 ad28 v_3 53 cas4#/dqm4 cas0#/dqm0 ad29 v_3 54 ma10 ma12 ad30 reserved 55 v_3s v_3s v_3s reserved 56 ma11 ma13 ad31 init# 57 md39 md07 c/be0# v_cpuio 58 md37 md02 c/be1# intr 59 md38 md00 c/be2# cpurst 60 gnd gnd gnd gnd 61 md36 md04 c/be3# stpclk# 62 md33 md01 ignne# smi# 63 md35 md03 ferr# nmi 64 md32 md06 a20m# v_5 65 md34 md05 v_cpuio v_cpuio 66 v_3s v_3s tdo trst# 67 oem_pd pclk itp0 tdi 68 fqs0 fqs1 itp1 tms 69 hclk1 hclk0 cpu3.3_2.5# tclk 70 gnd gnd gnd gnd
14 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 3.3 pin and pad assignments the mmc-1 surface mount connector has a 0.6-milimeter pitch and has 280 pins. for size information, refer to section 5.1.4 ?height restrictions?. figure 2 shows the connector pad assignments for the manufacturer?s system electronics. aa 70 aa 1 ab 70 ab 1 ba 70 ba 1 bb 70 bb 1 figure 2 . 280-pin connector footprint pad numbers, module secondary side
15 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz table 11 summarizes the key specifications for the mmc-1 connector. table 11 . connector specifications parameter condition specification material contact copper alloy housing thermo plastic molded compound: lcp electrical current 0.5 a voltage 50 vac insulation resistance 100 m w minimum at 200 vdc termination resistance 50 m w maximum capacitance 5 pf maximum per contact mechanical mating cycles 50 cycles connector mating force 3.2 oz per contact contact unmating force 0.35 oz per contact 4.0 functional description 4.1 celeron processor mobile module mmc-1 the celeron processor mobile module mmc-1 is offered at speeds of 466 megahertz and 433 megahertz. all processor speeds have a psb speed of 66 megahertz. 4.2 l2 cache the on-die l2 cache is 128 kilobytes, is four-way set associative, and runs at the speed of the processor core. 4.3 the 82443dx host bridge system controller intel?s 82443dx host bridge system controller combines the mobile celeron processor bus controller, the dram controller, and the pci bus controller into one component. the 82443dx host bridge has multiple power management features designed specifically for notebook systems such as: clkrun#, a feature that enables controlling of the pci clock on or off. the 82443dx host bridge suspend modes, which include suspend-to-ram (str), suspend-to-disk (std), and powered-on-suspend (pos). system management ram (smram) power management modes, which include compatible smram (c_smram) and extended smram (e_smram). c_smram is the traditional smram feature implemented in all intel pci chipsets. e_smram is a new feature that supports write-back cacheable smram space up to 1 megabyte. to minimize power consumption while the system is idle, the internal 82443dx host bridge clock is turned off (gated off). this is accomplished by setting the g_clk enable bit in the power management register in the 82443dx through the system bios. 4.3.1 memory orga nization the mmc-1 connector signaling interface supports the 82443dx host bridge standard mode, memory configurations, and modes of operation. this allows the memory interface to support the following: one set of memory control signals, sufficient to support up to three so-dimm sockets and six banks of sdram at 66 megahertz. one cke signal for each bank. memory features not supported by the 82443dx host bridge system controller standard mmc-1 mode are: support for eight banks of memory. second set of memory address lines (maa[13:0]). accelerated graphics port (agp). the 82443dx host bridge system controller supports dram technologies edo and sdram. these memory types should not be mixed in the system, so that all dram in all rows (ras[5:0]#) must be of the same technology. the 82443dx host bridge system controller targets 60-nanosecond edo drams, and 66-megahertz sdrams. the celeron processor mobile module?s clocking architecture supports the use of sdram. tight timing requirements of the 66-megahertz sdram clocks allow all host and sdram clocks to be generated from the same clocking architecture on the oem?s system electronics. for complete details about using sdram memory and for trace length guidelines, refer to the mobile pentium? ii processor / 82443bx pciset advanced platform recommended design and debug practices. refer to the intel a 440bx pciset datasheet f or details on memory device support, organization, size, and addressing. 4.3.2 reset strap options several strap options on the memory address bus define the behavior of the celeron processor mobile module mmc-1after reset. other straps are allowed to override the default settings. table 14 shows the various straps and their implementation.
16 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz table 12 . configuration straps for the 82443dx host bridge system controller signal function module default setting mab[12]# host frequency select no strap - 66-mhz default. mab[11]# in order queue depth no strap - maximum queue depth is set, i.e. 8. mab[10] quick start select strapped high on the module for quick start mode. mab[9]# agp disable strapped to disable agp. mab[7]# mm config strapped for mmc-1 compatible mode. mab[6]# host bus buffer mode select strapped high on the module for mobile psb buffers. 4.3.3 pci interface the pci interface of the 82443dx host bridge is available at the connector. the 82443dx host bridge supports the pci clockrun protocol for pci bus power management. in this protocol, pci devices assert the clkrun# open-drain signal when they require the use of the pci interface. refer to the pci mobile design guide for complete details on the pci clockrun protocol. the 82443dx host bridge is responsible for arbitrating the pci bus. with the mmc-1 connector the 82443dx host bridge can support up to five pci bus masters. there are five pci request/grant pairs, req[4:0]# and gnt[4:0]#, available to the manufacturer?s system electronics. the pci interface on the connector is 3.3 volts only. all devices that drive outputs to a 5.0 vt nominal v oh level are not supported. the 82443dx host bridge system controller is compliant with the pci 2.1 specification, which improves the worst case pci bus access latency from earlier pci specifications. as detailed in the pci specification, the 82443dx host bridge supports only mechanism #1 for accessing pci configuration space. this implies that signals ad[31:11] are available for pci idsel signals. however, since the 82443dx host bridge is always device #0, ad11 will never be asserted during pci configuration cycles as an idsel. the 82443dx reserves ad12 for the agpbus, which is not supported by the mmc-1 connector. thus, ad13 is the first available address line usable as an idsel. ad18 should be used by the piix4e/m. 4.3.4 agp feature set the intel mmc-1 family does not support the agp graphics port interface. for agp information, refer to the intel a celeron ? processor mobile module: mobile module connector 2 (mmc-2). 4.4 power management 4.4.1 clock control architecture the celeron processor mobile module?s clock control architecture is optimal for notebook designs. the clock control architecture consists of seven different clock states: normal, stop grant, auto halt, quick start, halt/grant snoop, sleep, and deep sleep. the auto halt state provides a low power clock state that can be controlled through the software execution of the hlt instruction. the quick start state provides a low power, low exit latency clock state that can be used for hardware controlled ?idle? computer states. the deep sleep state provides an extremely low power state that can be used for ?power-on suspend? states, which is an alternative to shutting off the processor?s power. the exit latency of the deep sleep state has been reduced to 30 microseconds. the stop grant and sleep states are not available on the celeron processor mobile module as these states are intended for desktop or server systems. the stop grant and the quick start clock states are mutually exclusive. for example a strapping option on signal a15# chooses which state is entered when the stpclk# signal is asserted. strapping the a15# signal to ground at reset enables the quick start state. otherwise, asserting the stpclk# signal puts the mobile celeron processor into the stop grant state. the stop grant s tate is useful for smp platforms and is not supported on the ce leron processor mobile module mmc-1. the quick start s tate is available on the module and provides a significantly lower power level. figure 3 provides an illustration of the clocking architecture. performing state transitions not shown in figure 3 is neither recommended nor supported. .
17 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz halt/grant snoop normal state hs=false stop grant auto halt hs=true quick start sleep deep sleep (!stpclk# and !hs) or stop break stpclk# and !qse and sga snoop occurs snoop serviced stpclk# and qse and sga (!stpclk# and !hs) or reset# snoop serviced snoop occurs !stpclk# and hs stpclk# and !qse and sga hlt and halt bus cycle halt break snoop serviced snoop occurs stpclk# and qse and sga !stpclk# and hs !slp# or reset# slp# bclk stopped bclk on and !qse bclk stopped bclk on and qse halt break ? a20m#, binit#, flush#, init#, intr, nmi, preq#, reset#, smi# hlt ? hlt instruction executed hs ? processor halt state qse ? quick start state enabled sga ? stop grant acknowledge bus cycle issued stop break ? binit#, flush#, reset# intel mobile modules do not support the shaded clock control states figure 3 . clock control states
18 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 4.4.2 normal state this is the normal operating mode. the processor?s core clock is running and the processor is actively executing instructions. 4.4.3 auto halt state this is a low power mode entered by the processor through the execution of the hlt instruction. the power level of this mode is similar to the stop grant state. a transition to the normal state is made by a halt break event (one of the following signals going active: nmi, intr, binit#, init#, reset#, flush#, or smi#). asserting the stpclk# signal while in the auto halt state will cause the processor to transition to the stop grant or quick start state, which issues a stop grant acknowledge bus cycle. deasserting stpclk# will cause the processor to return to the auto halt state without issuing a new halt bus cycle. the smi# (system management interrupt) is recognized in the auto halt state. returning from the smi handler can be to either the normal state or the auto halt state. see the intel ? architecture software developer?s manual, volume iii: system programmer?s guide for more information. no halt bus cycle is issued when returning to the auto halt state from system management mode (smm). the flush# signal is serviced in the auto halt state. after flushing the on-chip, the processor will return to the auto halt state without issuing a halt bus cycle. transitions in the a20m# and preq# signals are recognized while in the auto halt state. 4.4.4 stop grant state intel mobile modules do not support the stop grant state. the processor enters this mode with the assertion of the stpclk# signal when it is configured for stop grant state (via the a15# strapping option). the processor still responds to snoop requests and latch interrupts. latched interrupts will be serviced when the processor returns to the normal state. only one occurrence of each interrupt event will be latched. a transition back to the normal state can be made by the deassertion of the stpclk# signal or the occurrence of a stop break event (a binit#, flush#, or reset# assertion). the processor will return to the stop grant state after the completion of a binit# bus initialization unless stpclk# has been deasserted. reset# assertion will cause the processor to immediately initialize itself, but the processor will stay in the stop grant state after initialization until stpclk# is deasserted. if the flush# signal is asserted, the processor will flush the on-chip caches and return to the stop grant state. a transition to the sleep state can be made by the assertion of the slp# signal. while in the stop grant state, assertions of smi#, init#, intr, and nmi (or lint[1:0]) will be latched by the processor. these latched events will not be serviced until the processor returns to the normal state. only one of each event will be recognized upon return to the normal state. 4.4.5 quick start state this is a mode entered by the processor with the assertion of the stpclk# signal when it is configured for the quick start state (via the a15# strapping option). in the quick start state the processor is only capable of acting on snoop transactions generated by the psb priority device. because of its snooping behavior, quick start can only be used in single processor configurations. a transition to the deep sleep state can be made by stopping the clock input to the processor. a transition back to the normal state (from the quick start state) is made only if the stpclk# signal is deasserted. while in this state the processor is limited in its ability to respond to input. it is incapable of latching any interrupts, servicing snoop transactions from symmetric bus masters, or responding to flush# or binit# assertions. while the processor is in the quick start state, it will not respond properly to any input signal other than stpclk#, reset#, or bpri#. if any other input signal changes, then the behavior of the processor will be unpredictable. no serial interrupt messages may begin or be in progress while the processor is in the quick start state. reset# assertion will cause the processor to immediately initialize itself, but the processor will stay in the quick start state after initialization until stpclk# is deasserted. 4.4.6 halt/grant snoop state the processor will respond to snoop transactions on the psb while in the auto halt state, the stop grant state, or the quick start state. when a snoop transaction is presented on the psb the processor will enter the halt/grant snoop state. the processor will remain in this state until the snoop has been serviced and the psb is quiet. after the snoop has been serviced, the processor will return to its previous state. if the halt/grant snoop state is entered from the quick start state, then the input signal restrictions of the quick start state still apply in the halt/grant snoop state, except for those signal transitions that are required to perform the snoop. 4.4.7 sleep state intel mobile modules do not support the sleep state. the sleep state is a very low power state in which the processor maintains its context and the phase-locked loop (pll) maintains phase lock. the sleep state can only be entered from the stop grant state. after entering the stop grant state the slp# signal can be asserted, causing the processor to enter the sleep state. the slp# signal is not recognized in the normal state or the auto halt state. the processor can be reset by the reset# signal while in the sleep state. if reset# is driven active while the processor is in the sleep state, then slp# and stpclk# must immediately be driven inactive to ensure that the processor correctly initializes itself. input signals (other than reset#) may not change while the processor is in the sleep state or transitioning into or out of the sleep state. input signal changes at these times will cause unpredictable behavior. thus, the processor is incapable of snooping or latching any events in the sleep state. while in the sleep state the processor can enter its lowest power state, the deep sleep state. removing the
19 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz processor?s input clock puts the processor in the deep sleep state. picclk may be removed in the sleep state. 4.4.8 deep sleep state the deep sleep state is the lowest power mode the processor can enter while maintaining its context. stopping the bclk input to the processor enters sleep state. for proper operation, the bclk input should be stopped in the low state. the processor will return to the sleep state or the quick start state from the deep sleep state when the bclk input is restarted. due to the pll lock latency, there is a 30- millisecond delay after the clocks have started before this state transition happens. picclk may be removed in the deep sleep state. picclk should be designed to turn on when bclk turns on when transitioning out of the deep sleep state. the input signal restrictions for the deep sleep state are the same as for the sleep state, except that reset# assertion will result in unpredictable behavior. table 13 . clock state characteristics clock state exit latency processor power snooping system uses normal n/a varies yes normal program execution auto halt approximately 10 bus clocks 1.2w yes s/w controlled entry idle mode stop grant 1 10 bus clocks 1.2w yes h/w controlled entry/exit mobile throttling quick start through snoop , to halt/grant snoop state: immediate through stpclk #, to normal state: 10 bus clocks 0.5w yes h/w controlled entry/exit mobile throttling halt/grant snoop 1 a few bus clocks after the end of snoop activity. not specified yes supports snooping in the low power states sleep to stop grant state 10 bus clocks 0.5w no h/w controlled entry/exit desktop idle mode support deep sleep 30 msec 150 mw no h/w controlled entry/exit mobile powered-on suspend support notes: 1. intel mobile modules do not support shaded clock control states. 2. not 100% tested. specified at 50 c by design/characterization. 4.5 typical pos/str power table 14 lists the pos/str typical power specifications. table 14 . pos/str power state typical mmc-1 power pos 0.475w str 0.018w note: these are average values of measurement and are guidelines only. 4.6 electrical requirements the following section provides information on the electrical requirements for the celeron processor mobile module mmc-1. 4.6.1 dc requirements table 15 provides dc power supply design criteria. table 15 . power supply design specifications 1 symbol parameter min nom max unit notes v dc 2,3 dc input voltage 5.0 12.0 21.0 v i dc dc input current 0.1 0.9 3.5 a i dc-surge maximum surge current for v dc 17.3 a
20 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz symbol parameter min nom max unit notes i dc-leakage 4 typical leakage current for v dc 4.0 m a (at 25 c) v 5 power managed 5v voltage supply 4.75 5.0 5.25 v i 5 power managed 5v current 17 32 60 ma i 5-surge maximum surge current for v 5 0.6 a i 5-leakage typical leakage current for v 5 1.0 m a v 3 power managed 3.3v voltage supply 3.135 3.3 3.465 v i 3 power managed 3.3v current 0.8 1.2 2.0 a i 3-surge maximum surge current for v 3 2.8 a i 3-leakage typical leakage current for v 3 1.1 ma v 3s power managed 3.3v voltage supply 3.135 3.3 3.465 v i 3s power managed 3.3v current ? 0.35 0.5 ma i 3s-surge maxim um surge current for v 3s ? ? tbd a i 3s-leakage typical leakage current for v 3s tbd tbd tbd ma v cpupu processor i/o ring voltage 2.375 2.5 2.625 v 0.125 i cpupu 5 processor i/o ring current 0 10 20 ma v clk processor clock rail voltage 2.375 2.5 2.625 v 0.125 i clk 5 processor clock rail current 24.0 35.0 80.0 ma notes: 1. unless otherwise noted, all specifications in this table apply to all intel mobile module frequencies. 2. v_dc is set for 12v in order to determine typical v_dc current. 3. v_dc is set for 5v in order to determine maximum v_dc current. 4. leakage current that can be expected when vr_on is deactivated and v_dc is still applied. 5. these values are system dependent.
21 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 4.6.2 ac requirements table 16 provides the psb clock (bclk) ac requirements for the celeron processor mobile module mmc-1. table 16 . bclk ac specifications at the processor core pins 1,2,3 t# parameter min nom max unit figure notes psb frequency 4 66.67 mhz all processor core frequencies t1: bclk period 4,5 15.0 ns t2: bclk period stability 6,7,8 250 ps t3: bclk high time 5.3 ns at >1.8v t4: bclk low time 5.3 ns at <0.7v t5: bclk rise time 8 0.175 0.875 ns (0.9v-1.6v) t6: bclk fall time 8 0.175 0.875 ns (1.6v-0.9v) notes: 1. unless otherwise noted, all specifications in this table apply to all intel mobile modules. 2. all ac timings for the gtl+ signals are referenced to the bclk rising edge at 1.25v at the processor core pin. all gtl+ signal timings (address bus, data bus, etc.) are referenced at 1.00v at the processor core pins. 3. all ac timings for the cmos signals are referenced to the bclk rising edge at 1.25v at the processor core pin. all cmos signal timings (compatibility signals, etc.) are referenced at 1.25v at the processor core pins. 4. the internal core clock frequency is derived from the psb clock. the psb clock to core clock ratio is determined during initialization as described and is predetermined by the celeron processor mobile module. 5. the bclk period allows +0.5 ns tolerance for clock driver variation. see the ck97 clock synthesizer/driver specification for further information. 6. measured on the rising edge of adjacent bclks at 1.25v. the jitter present must be accounted for as a component of bclk skew between devices. 7. the clock driver?s closed loop jitter bandwidth must be set low to allow any pll-based device to track the jitter created by the clock driver. the -20 db attenuation point, as measured into a 10 pf to 20-pf load, should be less than 500 khz. this specification may be ensured by design characterization and/or measured with a spectrum analyzer. see the ck97 clock synthesizer/driver specification for further details. 8. not 100% tested. specified by design characterization as a clock driver requirement.
22 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 4.6.2.1 bclk signal quality specifications and measurement guidelines table 17 describes the signal quality specifications at the processor core for the bclk signal. figure 4 describes the signal quality waveform for the bclk at the processor core pins. table 17 . bclk signal quality specifications at the processor core t# parameter min max unit v1: bclk v il 2 0.7 v v2: bclk v ih 2 1.8 v v3: v in absolute voltage range 3 -0.8 3.5 v v4: r ising edge ringback 4 1.8 v v5: falling edge ringback 4 0.7 v bclk rising/falling slew-rate 0.8 4 v/ns notes: 1. unless otherwise noted, all specifications in this table apply to all intel mobile modules. 2. bclk must rise and fall monotonically between v il,bclk and v ih, bclk. 3. the mobile celeron processor psb clock overshoot and undershoot specification for 66-megahertz operation. 4. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the bclk signal can dip back to after passing the v ih (rising) or v il (falling) voltage limits. 5. for proper signal termination, refer to the clocking guidelines in the mobile pentium a ii processor / 440bx pciset advanced platform recommend design and debug practices. v2 v1 v3 v3 t3 v5 v4 t6 t4 t5 000806 figure 4 . bclk, tck, picclk generic clock waveform at the processor core pin 4.7 the voltage regulator the dc voltage regulator (dc/dc converter) provides the appropriate core voltage, the i/o ring voltage, and the sideband signal pullup voltage for the celeron processor mobile module. the voltage range is 5 volts-21 volts. 4.7.1 voltage regulator efficiency table 18 lists the voltage regulator efficiencies. table 18 . typical voltage regulator efficiency icore, a 3 v_dc, v i_dc, a 2 efficiency 1 1 5.0 0.370 82.8%
23 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 2 5.0 0.702 88.8% 3 5.0 1.044 89.8% 4 5.0 1.404 89.7% 5 5.0 1.762 88.1% 6 5.0 2.144 86.4% 7 5.0 2.528 85.0% 1 12.0 0.159 79.7% 2 12.0 0.295 87.0% 3 12.0 0.438 87.8% 4 12.0 0.584 87.3% 5 12.0 0.736 86.1% 6 12.0 0.890 84.9% 7 12.0 1.043 83.8% 1 21.0 0.091 79.3% 2 21.0 0.170 86.0% 3 21.0 0.253 87.3% 4 21.0 0.340 85.3% 5 21.0 0.429 84.1% 6 21.0 0.519 82.9% 7 21.0 0.617 80.7% notes: 1. these efficiencies will change with future voltage regulators that accommodate wider ranges of input voltages. 2. with v_dc applied and the voltage regulator off, typical leakage is 0.3 ma with a maximum of 0.7 ma. 3. icore indicates the cpu core current being drawn during test and measurement. 4.7.2. control of the voltage regulator the vr_on pin turns the dc voltage regulator on or off. the vr_on pin should be controlled as a function of the susb#, which controls the system?s power planes. vr_on should switch high only when the following conditions are met: v_5(s) => 4.5 volts and v_dc => 4.75 volts. caution - turning on vr_on prior to meeting these conditions will severely damage the celeron processor mobile module. the vr_pwrgd signal indicates that the voltage regulator power is operating at a stable voltage level. use vr_pwrgd on the system electronics to control power inputs and to gate pwrok to the piix4e/m. table 19 lists the voltage signal definitions and sequences, and figure 5 shows the signal sequencing and the voltage planes sequencing required for normal operation of the celeron processor mobile module mmc-1.
24 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 4.7.2.1 voltage signal definition and sequencing table 19 . voltage signal definitions and sequences signal source definitions and sequences v_dc system electronics dc voltage is driven from the power supply and is required to be between 5v and 21v dc. v_dc powers the module?s dc-to-dc converter for processor core and i/o voltages. it cannot be hot inserted or removed while v_dc is powered on. v_3 system electronics v_3 is supplied by the system electronics for the 82443dx. v_5 system electronics v_5 is supplied by the system electronics for the 82443dx?s 5v-reference voltage and the voltage regulator. v_3s system electronics v_3s is supplied by the system electronics. this is a 3.3v power supply that is turned off during suspend during system states str, std and soff. vr_on system electronics enables the voltage regulator circuit. when driven active high (3.3v) the voltage regulator circuit on the module is activated. the signal driving vr_on should be a digital signal with a rise/fall time of less than or equal to 1 m s. (vil (max)=0.4v, vih (min)=3.0v). v_core (also a host bus gtl+ termination voltage vtt) module a result of vr_on being asserted, v_core is an output of the dc-dc regulator on the module and is driven to the core voltage of the processor. it is also used as the host bus gtl+ termination voltage, known as vtt. v_bsb_io module v_bsb_io is 1.8v. the system electronics uses this voltage to power the l2 cache-to-processor interface circuitry. vr_pwrgd module upon sampling the voltage level of v_core (minus tolerances for ripple), vr_pwrgd is driven active high. if vr_pwrgd is not sampled active within 1 second of the assertion of vr_on, then the system electronics should deassert vr_on. after v_core is stabilized, vr_pwrgd will assert to logic high (3.3v). this signal must not be pulled up by the system electronics. vr_pwrgd should be ?anded? with v_3s to generate the piix4e/m input signal, pwrok. the system electronics should monitor vr_pwrgd to verify it is asserted high prior to the active high assertion of piix4e/m pwrok. v_cpuio module v_cpuio is 2.5v. the system electronics uses this voltage to power the piix4e/m-to-processor interface circuitry, as well as the hclk(0:1) drivers for the processor clock. the following list provides additional specifications and clarifications of the power sequence timing and figure 5 provides an illustration of the power sequence timing. 1. the vr_on signal may only be asserted to a logical high by a digital signal after v_dc 3 4.7 volts, v_5 3 4.5 volts and v_3 3 3.0 volts. 2. the rise time and fall time of vr_on must be less than or equal to 1 microsecond when it goes through its vil to vih. 3. vr_on has its vil(max) = +0.4 volts and vih(min) = +3.0 volts. 4. the vr_pwrgd will get asserted to logic high (3.3 volts) after v_core is stabilized and v_dc reaches 5.0 volts. this signal should not and can not be pulled up by the system electronics. 5. in the power-on process, intel recommends to raise the higher voltage power plane first (v_dc), followed by the lower power planes (v_5, v_3), and finally assert vr_on after above voltage levels are met on all rails. the power-off process should be the reverse process, i.e. vr_on gets deasserted, followed by the lower power planes, and finally the higher power plane. 6. vr_on must monotonically rise through its vil to vih and fall through its vih to vil points. the sign of slope can not change between vil and vih in rising and vih and vil in falling. 7. vr_on must provide an instantaneous in-rush current to the module with the following values as listed in table 20.
25 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz table 20 . vr_on in-rush current instantaneous dc operating max 41.0 ma 0.1 m a typ 0.2 ma 0.0 m a note: these values are based on a 3.3v vr_on signal. 8. vr_on valid-low time: this specifies how long vr_on needs to be low for a valid off before vr_on can be turned back on again. in going from a valid on to off and then back on, the following conditions must be met to prevent damage to the oem system or the intel mobile module: vr_on must be low for 1 millisecond. the original voltage level requirements for turn-on must be met before assertion of vr_on (i.e. v_dc 3 4.7 volts, v_5 3 4.5 volts, and v_3 3 3.0 volts). power sequence timing v_dc 1. pwrok on i/o board should be active on when vr_pwrgd is active and v_3s is good. 2. cpu_rst from i/o board should be active for a minimum of 6 ms after pwrok is active and pll_stp# and cpu_stp# are inactive. note that pll_stp# is an and condition of rsmrst# and susb# on the piix4e/m. 3. v_dc >= 4.7v, v_5>=4.5v, v_3s>=3.0v. 4. v_cpupu and v_clk are generated on the intel mobile module. 5. this is the 5v power supplied to the processor module connector. this should be the first 5v plane to power up. 6. vr_pwrgd is specified to its associated high/active by the module regulator within less than or equal to 6 ms max. after the assertion of vr_on. v_3 v_5 vr_pwrgd v_3s vr_on 0 ms min 0 ms min 0 ms min 6 3 v_cpupu/ v_clk 5 figure 5 . power-on sequence timing 4.7.3 power planes: bulk capaci tance requirements in order to provide adequate filtering and in-rush current protection for any system design, bulk capacitance is required. a small amount of bulk capacitance is supplied on the module. however, in order to achieve proper filtering additional capacitance should be placed on the system electronics. table 21 details the bulk capacitance requirements for the system electronics.
26 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz table 21 . capacitance requirements per power plane power plane capacitance requirements esr ripple current rating v_dc 100 uf, 0.1 uf, 0.01 uf 1 20 m w 1-3.5a 3 20% tolerance at 35v v_5 100 uf, 0.1 uf, 0.01 uf 1 100 m w 1a 20% tolerance at 10v v_3 470 uf, 0.1 uf, 0.01 uf 1 100 m w 1a 20% tolerance at 6v v_3s 100 uf, 0.1 uf, 0.01 uf 1 100 m w n/a 20% tolerance at 6v v_cpuio 2 2.2 uf, 8200 pf 1 n/a n/a 20% tolerance at 6v notes: 1. placement of above capacitance requirements should be located near the connector. 2. v_cpuio filtering should be located next to the system clock synthesizer. 3. ripple current specification depends on v_dc input. for 5.0v v_dc, a 3.5-a device is required. 4. for v_dc at 18v or higher, 1a is sufficient. 4.7.4 surge current guidelines this section provides the results of a worst case, surge current analysis. the analysis determines the maximum amount of surge current that the celeron processor mobile module mmc-1 can manage. in the analysis, the module has two 4.7 microfarads with an esr of 0.15 ohms total. the mmc-1 connector is approximately 30 milliohms of series resistance, for a total series resistance of .18 ohms. if the user powers the system with the a/c adapter (18 volts), the amount of surge current on the module would be approximately 100 amperes. this information is also used to develop i/o bulk capacitance requirements. see table 20 for more information. note : depending on the system electronics design, different impedances may yield different result. a thorough analysis should be performed to understand the implications of surge current on their system. figure 6 shows an electrical model used when analyzing instantaneous power-on conditions, and figure 7 illustrates the results with a spice simulation. figure 6 . instantaneous in-rush current model
27 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz figure 7 . instantaneous in-rush current due to the stringent component height requirements of the celeron processor mobile module, polymerized organic semiconductor capacitors must be used as input bulk capacitance in the voltage regulator circuit. because of the capacitor?s susceptibility to high in-rush current, special care must be taken. one way to soften the in-rush current and provide overvoltage and overcurrent protection is to ramp up v_dc slowly using a circuit similar to the one shown in figure 8.
28 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz note: values shown are for reference only . figure 8 . overcurrent protection circuit 4.7.4.1 slew-rate control: circuit description in figure 8, pwr is the voltage generated by applying the ac adaptor or battery. m1 is a low r ds (on) p-channel mosfet such as a siliconix* si4435dy. when the voltage- on pwr is applied and increased to over 4.75 volts, the under_voltage_lockout circuit allows r4 to pull up the gate of m3 to start a turn-on sequence. m3 pulls its drain toward ground, forcing current to flow through r2. m1 will not start to source any current until after t_delay with t_delay defined as: t_delay . . r2 c9 ln 1 vt vpwr vgs_max vgs_max . r16 r16 r2 vpwr the manufacturer?s vgs_max specification of 20 volts must never be exceeded. however, vgs_max must be high enough to keep the rds (on) of the device as low as possible. after the initial t_delay, m1 will begin to source current and v_dc will start to ramp up. the ramp up time, t_ramp, is defined as: t_ramp . . r2 c9 ln 1 vsat vgs_max t_delay maximum current during the voltage ramping is: i . ctotal vpwr t_ramp as shown in the circuit in figure 8: t_delay = 5.53 ms; t_tran = 14.0 ms; and i_max = 146 ma. figure 9 shows a spice simulation of the circuit in figure 8. to increase the reliability of the tantalum capacitors, use a slew-rate control circuit as described in figure 8 and voltage derate the capacitor about 50 percent. for example, for a
29 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz maximum input voltage of 18 volts, use a 35-volt, low esr capacitor with high ripple current capability. place five, 22- microfarad/35-volt capacitors on the baseboard directly at the v_dc pins of the connector. the slew-rate control circuit should also be applied to every input power source to the system v_dc to provide the most protection. if all power is logically ?or?ed? together at the pwr node, there is still a potential problem. for example, if a 3x3 li-ion battery pack is powering the system (12 volts at pwr), and the ac adaptor (18 volts) is plugged into the system, it will immediately source current to the pwr node and v_dc rapidly. this is because the slew-rate control is already on. therefore, the slew-rate control must be applied to every input power source to provide the most protection. figure 9 . spice simulation using in-rush protection (example only) 4.7.4.2 undervoltage lockout: circuit description (v_uv_lockout) the circuit shown in figure 8 provides an undervoltage protection and locks out the applied voltage to module to prevent an accidental turn-on at low voltage. the output of this circuit, pin 1 of the lm339 comparator, is an open- collector output. it is low when the applied voltage at pwr is less than 4.75 volts. this voltage can be calculated with the following equation with the voltage across d7 as 2.5 volts (d7 is a 2.5-volt reference generator). v_uv_lockout . vref 1 r17 . r18 r25 r18 r25 = v_uv_lockout 4.757 volts
30 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 4.7.4.3 overvoltage lockout: circuit description (v_ov_lockout) the celeron processor mobile module mmc-1is specified to operate with a maximum input voltage of 21 volts. this circuit locks out the input voltage if it exceeds the maximum 21 volts. the output of this circuit, pin 14 of the lm339 comparator, is an open collector output. it is low when the applied voltage at pwr is more than 21 volts. this voltage can be calculated with the following equation: v_ov_lockout . . vref r26 r26 r27 1 r24 r23 = v_ov_lockout 20.998 volt 4.7.4.4 overcurrent protection: circuit description figure 8 shows that the circuit detects an overcurrent condition and cuts off the input voltage applied to the celeron processor mobile module. this circuit has two different current limit trip points. this takes into account the different maximum current drain by the celeron processor mobile module at different input voltages. assuming the ac adaptor voltage is 18 volts and the battery is a 3x3 li-ion configuration with a minimum of 7.5 volts, the maximum current for the above circuit can be calculated using the following expression: with ac adaptor (i_wadaptor): i_wadaptor . vref vbe_q1 r14 r13 r1 i_wadaptor = 0.989 amp without ac adaptor (i_woadaptor): i_woadaptor . vref vbe_q1 . r14 r33 r14 r33 r13 r1 i_woadaptor = 2.375 amp 4.8 active thermal feedback table 22 i dentifies the addresses allocated for the smbus thermal sensor. table 22 . thermal sensor smbus address table function smbus address thermal sensor 1001 110 note: the thermal sensor used is compliant with smbus addressing. please refer to the pentium? ii processor thermal sensor interface specification .
31 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 4.9 thermal sensor configuration register the configuration register of the thermal sensor controls the operating mode (auto convert vs. standby) of the device. since the processor temperature varies dynamically during normal operation, auto convert mode should be used exclusively to monitor processor temperature. table 23 shows the format of the configuration register. if the run/stop bit is low, then the thermal sensor enters auto- conversion mode. if the run/stop bit is set high, then the thermal sensor immediately stops converting and enters standby mode. the thermal sensor will still perform temperature conversions in standby mode when it receives a one-shot command. however, the result of a one-shot command during auto convert mode is not guaranteed. intel does not recommend using the one-shot command to monitor temperature when the processor is active, only auto convert mode should be used. refer to the mobile pentium ? ii processor and pentium ? ii processor mobile module thermal sensor interface specifications . table 23 . thermal sensor configuration register bit name reset state function 7 msb mask 0 masks smbalert# when high. 6 run/stop 0 standby mode control bit. if low, the device enters auto convert mode. if high, the device immediately stops converting, and enters standby mode where the one- shot command can be performed. 5-0 rfu 0 reserved for future use. note: all rfu bits should be written as ?0? and read as ?don?t care? for programming purposes. 5.0 mechanical specification this section provides the physical dimensions for the celeron processor mobile module mmc-1. 5.1 module dime nsions figure 10 shows the board dimensions and the orientation for the celeron processor mobile module mmc-1. figure 10 . celeron processor mobile module mmc-1 board dimensions
32 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 5.1.1 mmc-1 connector pin 1 location figure 11 shows the location of pin 1 of the connector as referenced to the adjacent mounting hole. figure 11 . celeron processor mobile module mmc-1 board dimensions- pin 1 orientation 5.1.2 printed circuit board thickness figure 12 shows the minimum and maximum thickness of the printed circuit board (pcb). the range of pcb thickness allows for the use of different pcb technologies with current and future intel mobile modules. note: ensure that the mechanical restraining method or system-level emi contacts are able to support this range of pcb thickness for compatibility with future intel mobile modules.
33 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz min: 0.90 mm max: 1.10 mm printed circuit board figure 12 . printed circuit board thickness 5.1.3 height restrictions figure 13 shows the mechanical stack-up and the associated component clearance requirements. this is referred to as the module keep-out zone and should not be entered or altered. the system manufacturer establishes the board-to-board clearance between the module and the system electronics by selecting one of three possible mating connectors. the mating connector sizes are 4 millimeters, 6 millimeters, or 8 millimeters. these three options provide the system manufacturer with flexibility in choosing components between the two boards. information on these connectors can be obtained from your local intel representative. note : the topside component clearance is independent of the pcb thickness. figure 13 . keep-out zone 5.2 thermal transfer plate the ttp on the cpu and the 82433bx provides heat dissipation and a thermal attach point where a system
34 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz manufacturer can attach a heat pipe, a heat spreader plate, or a thermal solution to transfer heat through the notebook system. see figure 14 and figure 15 for attachment dimensions from the thermal interface block to the ttp. when attaching the mating block to the ttp, a thermal elastomer or thermal grease should be used. this material reduces the thermal resistance. the oem thermal interface block should be secured with 2.0-millimeter screws using a maximum torque of 1.5 kg*cm to 2.0 kg*cm (equivalent to 0.147 n*m to.197 n*m). the thread length of the 2.00- millimeter screws should be 2.25-millimeter gageable thread (2.25-millimeters minimum to 2.80-millimeters maximum). the system manufacturer should use the exact dimensions for maximum contact area to the ttp to ensure that no warpage of the ttp occurs. if warpage occurs, the thermal resistance of the module could be adversely affected. the ttp thermal resistance between the processor core to the system interface (top of the ttp) is less than 1 celsius per watt. figure 14 . thermal transfer plate (a)
35 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz figure 15 . thermal transfer plate (b) 5.3 physical support 5.3.1 mounting requirements three mounting holes are available for securing the module to the system base. see figure 11 for mounting hole locations. these hole locations and board edge clearances will remain fixed for all intel mobile modules. intel recommends that all three mounting holes are used to ensure long term mechanical reliability and emi integrity of the system. the board edge clearance includes a 0.762 millimeters (0.030 inches) wide emi containment ring around the perimeter of the module. this ring is on each layer of the module pcb and is grounded. on the surface of the module, the metal is exposed for emi shielding purposes. the hole patterns placed on the module also have a plated surrounding ring, which can be used with a metal standoff for emi shielding purposes. standoffs should be used to provide support for the installed celeron processor mobile module. the distance from the bottom of the module pcb to the top of the oem system electronics board with the connectors mated is 4.0 millimeters +0.16 millimeters / -0.13 millimeters. however the warpage of the baseboard can vary and should be calculated into the final dimensions of the standoffs used. all calculations can be made with the intel a mmc-1 standoff/receptacle height spreadsheet . information on this spreadsheet can be obtained from your local intel representative. figure 16 shows the standoff support hole patterns, the board edge clearance, the dimensions of the emi containment ring, and the keep-out area.
36 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz hole detail, 3 places 0.762 mm width of emi containment ring 1.27+/- 0.19 mm board edge to emi ring 2.54+/-0.19 mm keep-out area 3.81+/-0.19 mm board edge to hole centerline 3.81+/-0.19 mm 4.45 mm diameter grounded ring + 0.050 mm - 0.025 mm hole diameter 2.413 mm figure 16 . standoff holes, board edge clearance, and emi containment ring (topside) 5.3.2 module weight the celeron processor mobile module mmc-1 weighs approximately 50 grams. 6.0 thermal specification 6.1 thermal design power the typical tdp is the typical total power dissipation under normal operating conditions at nominal v_core (cpu power supply) while executing the worst case power instruction mix. the power handling capability of the system thermal solution may be reduced less than the recommended typical thermal design power with the implementation of firmware/software control or ?throttling? that reduces cpu power consumption and dissipation. this includes the power dissipated by all of the relevant components. during all operating environments, the processor junction temperature, t j , must be within the range of 0 celsius to 100 celsius. 6.2 thermal sensor setpoint the thermal sensor implements the smbalert# signal described in the smbus specification. smbalert# is always asserted when the temperature of the processor core thermal diode or the thermal sensor internal temperature exceeds either the upper or lower temperature thresholds. smbalert# may also be asserted if the measured temperature equals either the upper or the lower threshold. table 24 . thermal design power specifications symbol parameter typical notes tdp module cpu thermal design power 14.3 tdp module bx thermal design power 2.3 tdp module module thermal design power 17.4 module tdp = core, 82433bx, and voltage regulator note: 1. during all operating environments, the processor temperature, t j must be within the specified range of 0 celsius to 100 celsius. 2. tdp module is a thermal solution design reference point for oem thermal solution readiness for total module power.
37 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 7.0 labeling information the celeron processor mobile module mmc-1 is tracked in two ways. the first is by the product tracking code (ptc). intel uses the ptc label to determine the assembly level of the module. the ptc label is on the secondary side of the module as shown in figure 17 . the ptc consists of 13 characters and contains the following information: example: pmh4661001aa definition: aa - processor module = pm b - celeron processor mobile module mmc-1= h ccc - speed identity = 433, 466 dd - cache size = 01 (128k) eee - notifiable design revision (start at 001) ff - notifiable processor revision (start at aa) note: for the celeron processor mobile module (mmc-2) the second field (b) is defined as i figure 17 . product tracking code the second tracking method is by oem generated software utility. four strapping resistors located on the celeron processor mobile module mmc-1determine its production level. if connected and terminated properly, up to 16 module- revision levels can be determined. an oem generated software utility can then read these id bits with cpu ids and stepping ids to provide a complete module manufacturing revision level. for current ptc and module id bit information, please refer to the latest product change notification letter, which can be obtained from your local intel sales representative.
38 celeron ? processor mobile module mmc-1 at 466 mhz and 433 mhz 8.0 environ mental standards the environmental standards for the celeron processor mobile module mmc-1 are defined in table 25. table 25 . environmental standards parameter condition specification temperature non-operating -40 c to 85 c cycle operating 0 c to 55 c humidity unbiased 85% relative humidity at 55 c voltage v_5 5v +/- 5% v_3 3.3v +/- 5% shock non-operating half sine, 2g, 11 msec unpackaged trapezoidal, 50g, 11 msec packaged inclined impact at 5.7 ft/s packaged half sine, 2 msec at 36 in. simulated free fall vibration unpackaged 5 hz to 500 hz 2.2 grms random packaged 10 hz to 500 hz 1.0 grms packaged 11,800 impacts 2 hz to 5 hz (low frequency) esd damage human body model non-powered test of the module only for non- catastrophic failure. the module is tested at 2 kv and then inserted in a system for a functional test.

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